LYCOS RETRIEVER 
Instruction Register
built 656 days ago
The return address latch 608 passes the address of the instruction following the delayed instruction of a call to the register file. This address is the return address of the call. This is provided for special instruction implemented in the preferred embodiment designated CALL, which places the address of the second following instruction of the call instruction into the location designated in the call instruction. Then a non-sequential instruction fetch occurs, to an instruction address given by an operand designated in the call instruction. A delay instruction immediately following the call instruction is executed before the non-sequential fetch occurs.
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The control unit decodes the instruction, recognises it as an arithmetic instruction and directs the register file to drive the contents of register 1 onto the A input of the ALU and the contents of register 3 onto the B input. At the same time, it instructs the ALU to add its inputs.
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INTEST – the INTEST instruction causes the TDI and TDO lines to be connected to the Boundary Scan Register (BSR). While the EXTEST instruction allows the user to set and read pin states, the INTEST instruction relates to the core-logic signals of a device.
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The store cycle is when the result of the instruction is written to its destination, either a register or a memory location. This is really part of the execute cycle because some instructions may write to multiple destinations as part of their execution.
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Instruction Register